Designing Digital Computer Systems with Verilog
David J. Lilja
Sachin S. Sapatnekar
Cambridge University Press, New York, NY, 2005
Designing Digital Computer Systems with Verilog serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model, and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioral and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practicing engineers.
A list of corrections for the book.
This web site contains a variety of supplemental materials for use with this book. This material includes Verilog source code for the examples in the book, the Verilog source code for the behavioral and pipelined models of VeSPA, the source code for the VASM assembler, and some test programs. We also have included some material supplied by people who have developed some additional tools that you may find useful when working with VeSPA.
We are continually looking for new VeSPA-related material to add to this page. Please contact us through the links to our web sites above if you have some material that you would like us to consider including.
All of this material is supplied on an as-is basis with no warranty of any type. This material may be used for personal and educational purposes only. Any other use requires the explicit written permission of the authors.
Examples and materials from the book.
File Description verilog-ex.tar The Verilog examples from Chapter 2. vespa.tar The Verilog source code for the behavioral (Chapter 4) and pipelined (Chapter 7) versions of VeSPA; testbench programs (Chapter 8); the source code for VASM (Chapter 5 and Appendix B); some example assembly language programs.
Materials supplied by other contributors.
File Description Contributor self-test.asm A fairly comprehensive self-test program for VeSPA written in assembly language. Leon Gregg vcc-1p0.tar A C compiler that generates VeSPA assembly language. Note that for C programs that use pointers or arrays, this compiler will generate assembly code assuming that VeSPA has been extended with some additional instructions, such as a multiply instruction (MLT). For simple C programs, though, this compiler will generate assembly code that can be assembled and simulated using VASM and VeSPA as shown in the book. Mike Tobin rtio.tar RTIO adds a simple I/O capability to VeSPA using Verilog's PLI (Programming Language Interface). Note that the example behavioral.v file suppled in this distribution is an older version that does not include the XOR instruction. Daniel Tian userIO.tar Another approach for adding I/O to VeSPA using Verilog's PLI. This behavioral.v also does not include the XOR instruction. Andy Peng
Miscellaneous information about Verilog
- verilog.org -- A lot of information about Verilog.
- verilog.com -- More Verilog information.
- verilog.net -- Another web site devoted to Verilog.
- www.verilog.com/IEEEVerilog.html -- The IEEE Verilog standards web page.
- Finally, go to your favorite search engine and do a search on the keyword "Verilog." You will find many good Verilog resources.