This work is investigating a novel approach for computation called stochastic logic. The conventional approach for designing processors has been rigidly hierarchical with sharp boundaries between different levels of abstraction. From the logic level up, the Boolean functionality of the system is fixed and deterministic. Stochastic computing, on the other hand, conceptually transforms probability values into probability values, although it still relies on conventional Boolean logic gates as the underlying substrate.
Stochastic computing is particularly applicable for data intensive applications, such as signal and image processing and dynamic control systems, where small output fluctuations can be tolerated but large errors can be catastrophic. Additionally, with the increased scaling of semiconductor devices, soft errors in the logic circuits caused by ionizing radiation are a major concern, particularly for circuits operating in harsh environments such as space. Existing fault tolerance methods mitigate against bit-flips with system-level techniques, such as error-correcting codes and modular redundancy. The stochastic approach, in constrast, naturally tolerates bit errors due to its probablistic information encoding while producing savings in computational resources and power consumption compared to conventional approaches.
- M. Hassan Najafi, David J. Lilja, Marc Riedel, and Kia Bazargan, "Polysynchrous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits," IEEE Transactions on Computers, (to appear).
- M. Hassan Najafi, Shiva Jamalizavareh, David J. Lilja, Marc Riedel, Kia Bazargan, and Ramesh Harjani, "Time-Encoded Values for Highly Efficient Stochastic Circuits, "IEEE Transactions on Very Large Scale Integration (TVLSI), Vol. 25, No. 5, May, 2017, pp. 1644-1657.
- M. Hassan Najafi and David J. Lilja, "High-Speed Stochastic Circuits Using Synchronous Analog Pulses," Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2017.
- Peng Li and David J. Lilja, “A Low Power Fault-Tolerance Architecture for Kernel Density Estimation-Based Image Segmentation Algorithm,” IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), September, 2011.
- Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, “Synthesizing Combinational Logic to Generate Probabilities: Theories and Algorithms,” Advances in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati (eds.), Springer Publishing, 2011.
- Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, and David J. Lilja, “An Architecture for Fault-Tolerant Computation with Stochastic Logic,” IEEE Transactions on Computers, Vol. 60, No. 1, January, 2011, pp. 93-105.
- Weikang Qian, Marc D. Riedel, Kia Bazargan and David J. Lilja, “The Synthesis of Combinational Logic to Compute Probabilities,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2009, pp. 367-374.
- Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, “A Reconfigurable Stochastic Architecture for Highly Reliable Computing,” ACM Great Lakes Symposium on VLSI (GLSVLSI), May, 2009, pp. 315-320.