Processor design with emerging technologies

A variety of new technologies are being proposed for future processors, such as spintronic components, carbon nanotubes, and graphene. We are investigating how processors can be efficiently designed to best take advantage of these new technologies.

For example, working with other researchers in the Center for Spintronic Materials, Interfaces, and Novel Architectures (C-SPIN), we are investigating novel architectural solutions that take advantage of the unique functionality that can be achieved using a spin-based technology. The operation of conventional charge-based electronic transistor systems is based on the storage and transfer of electrons in the form of an electric charge or a current. It has been projected that by about 2020, charge-based devices will reach fundamental limits of speed, size, energy, and noise immunity. Spintronics devices, in contrast, are based on the up or down "spin" of electrons rather than on charges. The state of a spintronics device can be changed by controlling the magnetic fields generated by currents on the device's input lines. These spin states can be mapped to the binary logic states of a digital computing system. Because of the unique characteristics of spintronics devices, a processor constructed from these new devices potentially could be faster, provide superior heat dissipation characteristics, and have greater device density than a processor constructed from conventional charge-based devices. Furthermore, the information stored in the processor would be non-volatile allowing it to immediately continue executing from its previous state when the power is cycled. It also is expected that these devices will be more resistant to all types of internally and externally generated noise than conventional transistor devices making them more resistant to radiation-induced upsets, power supply variations, and signal cross-talk.

 

Selected papers

  • Cong Ma, William Tuohy, and David J. Lilja, "The Impact of Spintronic Memory on Multicore Cache Hierarchy Design," IET Computers and Digital Techniques, Vol. 11, No. 2, February, 2017, pp. 51-59.
  • Jongyeon Kim, Bill Tuohy, Cong Ma, Won Ho Choi, Ibrahim Ahmed, David Lilja, and Chris H. Kim, "Spin-Hall Effect MRAM Based Cache Memory: A Feasibility Study," Device Research Conference (DRC), June, 2015.
  • Cong Ma, William Tuohy, Pushkar Nandkar, David J. Lilja, "Implementing a Cycle-accurate STT-MRAM Model into the Gem5 Ruby Memory System," Second Gem5 User Workshop at the International Symposium on Computer Architecture (ISCA), June, 2015.
  • Shruti Patil and David J. Lilja, "A Programmable and Scalable Technique to Design Spintronic Logic Circuits Based on Magnetic Tunnel Junctions,” ACM Great Lakes Symposium on VLSI (GLSVLSI), May, 2011.
  • Shruti Patil and David J. Lilja, “Performing Bitwise Logic Operations In Memory Using Spintronics-Based Magnetic Tunnel Junctions,” ACM International Conference on Computing Frontiers, May, 2011.
  • Shruti Patil and David J. Lilja, “Spintronics-Based Logic Circuits Using Magnetic Tunnel Junctions,” Non-Volatile Memories Workshop (NVMW), March, 2011.
  • Shruti Patil, Andrew Lyle, Johathan Harms, David J. Lilja, and Jianping Wang, “Spintronic Logic Gates for Spintronic Data Using Magnetic Tunnel Junctions,” International Conference on Computer Design (ICCD), October, 2010.
  • Shruti R. Patil, Xiaofeng Yao, Hao Meng, Jian-Ping Wang, and David J. Lilja, “Design of a Spintronic Arithmetic and Logic Unit Using Magnetic Tunnel Junctions,” ACM International Conference on Computing Frontiers, May, 2008.
  • Min-Woo Jang, Chia-Ling Chen, Walter E. Partlo, Shruti R. Patil, Dongjin Lee, Zhijang Ye, David J. Lilja, T. Andrew Taton, Tianhong Cui, and Stephen A. Campbell, “A Pure Single-Walled Carbon Nanotube Thin Film Based Three-Terminal Microelectromechanical Switch,” Applied Physics Letters (APL), Vol. 98, No. X, 2011.
  • Andrew Lyle, Jonathan Harms, Shruti Patil, Xiaofeng Yao, David J. Lilja, and Jian-Ping Wang, “Direct Communication Between Magnetic Tunnel Junctions for Non-Volatile Logic Fan-Out Architecture,” Applied Physics Letters (APL), Vol. 97, No. 15, October 11, 2010.
  • Min-Woo Jang, Chia-Ling Chen, Walter E. Partlo III, Shruti a Patil, Dongjin Lee, Zhijang Ye, David J. Lilja, T. A. Taton, T. Cui and Stephen A. Campbell, “A Three-terminal Single-walled Carbon Nanotube Thin Film MEMS Switch for Digital Logic Applications,” International Conference on Solid-State Sensors, Actuators, and Microsystems (TRANSDUCERS), June, 2011.