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Recent research papers and technical reports.
-
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods,
Drew C. Ness and David J. Lilja,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 07-12, December, 2007.
(Presented at Design, Automation and Test in Europe (DATE),
March, 2008.)
-
SARD: A Statistical Approach for Ranking Database Tuning Parameters,
Biplob K. Debnath, James Skarie, David J. Lilja, and Mohamed F. Mokbel,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 07-11, October, 2007.
-
Improving Nanoelectronic Designs Using a Statistical Approach to
Identify Key Parameters in Circuit Level SEU Simulations,
Drew C. Ness, Christian J. Hescott, and David J. Lilja,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 07-10, September, 2007.
(Presented at the
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),
October, 2007.)
-
Analysis of Statistical Sampling in Microarchitecture Simulation: Metric,
Methodology and Program Characterization,
,
Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Wei-Chung Hsu,
and Pen-Chung Yew,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 07-09, July, 2007.
(Presented at the IEEE International
Symposium on Workload Characterization (IISWC), October, 2007.)
-
SCRAP: A Statistical Approach for Creating a Database Query Workload
Based on Performance Bottlenecks,
James Skarie, Biplob K. Debnath, David J. Lilja, and Mohamed F. Mokbel,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 07-08, July, 2007.
(Presented at the IEEE International
Symposium on Workload Characterization (IISWC), October, 2007.)
-
MMV: Metamodeling Based Microprocessor Validation Environment
,
Ajit Dingankar, Deepak A. Mathaikutty, Sreekumar V. Kodakara,
Sandeep K. Shukla and David J. Lilja,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 07-07, April, 2007.
(Presented at the IEEE International
High Level Design Validation and Test Workshop (HLDVT), 2006.)
-
Model Based Test Generation for Microprocessor Architecture Validation
,
Sreekumar V. Kodakara, Deepak A. Mathaikutty, Ajit Dingankar, Sandeep K.
Shukla and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 07-06, April, 2007.
(Presented at the IEEE
International Conference on VLSI Design (VLSI Design), 2007.)
-
A Probabilistic Analysis For Fault Detectability of Code Coverage
Metrics
,
Sreekumar V. Kodakara, Deepak A. Mathaikutty, Ajit Dingankar,
Sandeep K. Shukla and David J. Lilja,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 07-05, April, 2007.
(An abridged version of this paper was presented at the
IEEE Microprocessor Test and
Verification Workshop (MTV), 2006.)
-
Design Fault Directed Test Generation for Microprocessor Validation
,
Deepak A. Mathaikutty, Sreekumar V. Kodakara, Ajit Dingankar, Sandeep K.
Shukla and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 07-04, April, 2007.
(Presented at the IEEE Design, Automation and Test in Europe (DATE),
April, 2007.)
- CIM: A Reliable
Metric for Evaluating Program Phase Classifications,
Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Douglas Hawkins,
Wei-Chung Hsu, and Pen-Chung Yew,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 07-03,
April, 2007.
- NORTHSTAR:
A Parameter Estimation Method for the Spatial Autoregression Model,
Mete Celik, Baris M. Kazar, Shashi Shekhar, Daniel Boley, and David J. Lilja,
Department of Computer Science Report Number 07-004,
February, 2007.
-
Exploring Subsets of Standard Cell Libraries to Exploit
Natural Fault Masking Capabilities for Reliable Logic,
Drew C. Ness, Christian J. Hescott, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 07-02,
January, 2007.
(Presented at the
ACM Great Lakes Symposium on VLSI (GLSVLSI),
March, 2007.)
-
MEMESTAR: A Simulation Framework for Reliability Evaluation
Over Multiple Environments,
Christian J. Hescott, Drew C. Ness, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 07-01,
January, 2007.
(Presented at the
International Symposium on Quality Electronic Design (ISQED),
March, 2007.)
-
Cross-Layer Speculative-Parallelization Protocol Architecture for End
Systems and Gateways in Computer Networks With Lossy Links,
Haowei Bai, David J. Lilja, and Mohammed Atiquzzaman,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 06-08,
October, 2006.
-
Modeling Failure Reduction
for Combinational Logic using Gate Level NMR,
Drew C. Ness, Christian J. Hescott, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 06-07,
September, 2006.
(Presented at the
Annual Reliability and Maintainability Symposium (RAMS),
January, 2007.)
-
Evaluating Benchmark Subsetting Approaches,
Joshua Yi, Resit Sendag, Lieven Eeckhout, Ajay Joshi,
David J. Lilja, and Lizy John,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 06-06,
September, 2006.
(Presented at the IEEE International Symposium on
Workload Characterization (IISWC), October, 2006.)
-
The Exigency of Benchmark and Compiler Drift: Designing Tomorrow's
Processors with Yesterday's Tools,
Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 06-05,
January, 2006.
(Presented at the ACM International Conference on Supercomputing (ICS),
June, 2006.)
-
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies,
and Recommendations
,
Joshua J. Yi and David J. Lilja,
IEEE Transactions on Computers,
Vol. 55, No. 3, March, 2006, pp. 268-280.
- Applying
Speculative Parallelization to the Protocol Design for Networks With
Lossy Links,
Haowei Bai,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 06-04,
February, 2006. (Ph.D. in Electrical Engineering thesis.)
[Please contact Professor Lilja for a copy.]
-
Evaluating the Efficacy of Statistical Simulation for
Design Space Exploration,
Ajay Joshi, Joshua J. Yi, Robert H. Bell Jr., Lieven Eeckhout,
Lizy K. John, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 06-03,
January, 2006.
(Presented at the IEEE International Symposium on Performance Analysis
of Systems and Software (ISPASS),
March, 2006.)
-
Comparing Simulation Techniques for Microarchitecture-Aware Floorplanning
,
Vidyasagar Nookala, Ying Chen, David J. Lilja, and Sachin Sapatnekar,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 06-02,
January, 2006.
(Presented at the IEEE International Symposium on Performance Analysis
of Systems and Software (ISPASS),
March, 2006.)
-
Analyzing the Processor Bottlenecks in SPEC CPU 2000,
,
Joshua J. Yi, Ajay Joshi, Resit Sendag, Lieven Eeckhout, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 06-01,
January, 2006.
(Presented at the SPEC Benchmark Workshop,
January, 2006.)
-
A Methodology for Stochastic Fault Simulation
in VLSI Processor Architectures,
Christian J. Hescott, Drew C. Ness, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-16,
June, 2005.
(Presented at the Workshop on Modeling, Benchmarking and Simulation (MoBS),
June, 2005.)
-
Improving Computer Architecture Simulation Methodology by
Adding Statistical Rigor,
,
Joshua J. Yi, David J. Lilja, and Douglas M. Hawkins,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-14,
October, 2005.
(Appeared in IEEE Transactions on Computers,
Vol. 54, No. 11, Nov. 2005, pp. 1360-1373.)
-
Accurate Statistical Approaches for Generating Representative
Workload Compositions,
Lieven Eeckhout, Rashmi Sundareswara, Joshua J. Yi, David J. Lilja,
and Paul Schrater,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-15,
October, 2005.
(Appeared at the IEEE International Symposium on Workload Characterization
(IISWC), October, 2005.)
Please see the
correction
to this paper.
- Layered
View of QoS Issues in IP-Based Mobile Wireless Networks,
Haowei Bai, Mohammed Atiquzzaman, and David J. Lilja,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 05-13,
July, 2005.
(Published in Wiley International Journal of Communication Systems, Special
Issue on Radio Resource Management for Provisioning IP-Based QoS
in Wireless Cellular Networks, No. 19, 2006, pp. 141-161.)
- Applying
Speculative Technique to Improve TCP Throughput Over Lossy Links,
Haowei Bai, David Lilja, and Mohammed Atiquzzaman,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 05-12,
July, 2005.
(Presented at IEEE GLOBECOM 2005, St. Louis, MO,
November 28-December 2, 2005.)
- High
Performance Spatial Data Mining: Scalable
Methods for Spatial Autoregression,
Baris M. Kazar,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 05-11,
June, 2005. (Ph.D. in Electrical Engineering thesis.)
- Exploring
Design Issues for Large-Scale Distributed Systems: Data
and Resource Managements,
Keqiang Wu,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 05-10,
May, 2005. (Ph.D. in Electrical Engineering thesis.)
-
The SEASONing Tool: A Spice Engine for Adding Soft-errors On Netlists
,
Kevin KleinOsowski, AJ KleinOsowski, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-09,
May, 2005.
-
Improving TCP Throughput over Lossy Links using Protocol-Level Speculation,
,
Haowei Bai, David J. Lilja, and Mohammed Atiquzzaman,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-07,
May, 2005.
(Presented at
IEEE International Conference on Wireless Networks,
Communications, and Mobile Computing (WirelessCom),
June, 2005.)
-
Buffer Requirements at ECN-capable RED Gateways to Minimize Packet Losses,
,
Haowei Bai and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-06,
May, 2005.
(Presented at
IEEE Electro/Information Technology Conference,
May, 2005.)
-
Wireless Sensor Network for Aircraft Health Monitoring,
,
Haowei Bai, Mohammed Atiquzzaman, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-05,
May, 2005.
(Presented at
BroadNets Wireless Networking Symposium,
October, 2004.)
-
Using ECN Marks to Improve TCP Performance over Lossy Links
,
Haowei Bai, Mohammed Atiquzzaman, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-04,
May, 2005.
(Presented at
the International Conference on E-business and Telecommunication
Networks (ICETE),
August, 2004.)
-
Microarchitecture-aware floorplanning using a
statistical design of experiments approach
,
Vidyasagar Nookala, Ying Chen, David J. Lilja, and Sachin S. Sapatnekar,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-03,
April, 2005.
(Presented at the Design Automation Conference (DAC),
June, 2005.)
-
The Applicability of Adaptive Control Theory to QoS Design: Limitations
and Solutions
,
Keqiang Wu, David J. Lilja, and Haowei Bai,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-02,
January, 2005.
(Presented at the International Workshop on Performance Modeling,
Evaluation, and Optimization of Parallel and Distributed Systems
(PMEO-PDS), April, 2005.)
-
Communicating Quality of Service Requirements
to an Object-Based Storage Device
,
Kevin KleinOsowski, Tom Ruwart, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 05-01,
January, 2005.
(Presented at the NASA Goddard Conference on Mass Storage Systems and
Technologies (MSST 2005), April, 2005.)
-
Characterizing and Comparing Prevailing Simulation Techniques
,
Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag,
David J. Lilja, and Douglas M. Hawkins,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 04-06,
November, 2004.
(An abridged version of this report was presented at the
International Symposium on High-Performance Computer Architecture (HPCA),
February, 2005.)
-
Comparing Exact and Approximate Spatial Auto-Regression Model
Solutions for Spatial Data Analysis
,
B. M. Kazar, S. Shekhar, D. J. Lilja, R. R. Vatsavai, and R. K. Pace,
Army High-Performance Computing
Research Center (AHPCRC) Technical Report no. 2004-126.
-
State Pruning for Generating Efficient Test Vectors
,
Ying Chen, Dennis Abts, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 04-05,
July, 2004.
-
Self-tuning Speculation for Maintaining the
Consistency of Client-Cached Data
,
Keqiang Wu and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 04-04,
April, 2004.
(A condensed version of this paper was presented at the
International Conferance on Parallel and Distributed Systems (ICPADS),
July, 2004.)
- State
Pruning for Test Vector Generation for a Multiprocessor
Cache Coherence Protocol,
Ying Chen, Dennis Abts, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 04-03,
March, 2004.
(Presented at the
International
Workshop on Rapid System Prototyping,
June, 2004.)
-
A Parallel Formulation of the Spatial Auto-Regression Model for
Mining Large Geo-Spatial Databases,
B.M. Kazar, S.Shekhar, D.J. Lilja, and D. Boley,
Army High-Performance Computing Research Center (AHPCRC)
Technical Report no. 2004-103, March, 2004.
(Presented at the International Workshop on
High Performance and Distributed Mining (HPDM),
April, 2004.)
- Enhancing
the Memory Performance of Embedded Systems with the
Flexible Sequential and Random Access Memory,
Ying Chen, Karthik Ranganathan, Amit K. Puthenveetil,
Vasudev V. Pai, David J. Lilja, and Kia Bazargan,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 04-02,
March, 2004.
- FSRAM:
Flexible Sequential and Random Access Memory for Embedded Systems,
Ying Chen, Karthik Ranganathan, Amit K. Puthenveetil,
Kia Bazargan, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 04-01,
February, 2004.
- Exploring
Speculative Techniques to Improve the Memory System Performance,
Resit Sendag,
Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 03-08,
December, 2003. (Ph.D. in Electrical Engineering thesis.)
- The
Recursive NanoBox Processor Grid: A Reliable
System Architecture for Unreliable Nanotechnology Devices,
AJ KleinOsowski, Kevin KleinOsowski,
Vijay Rangarajan, Priyadarshini Ranganath, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 03-07,
December, 2003.
(Presented at the IEEE Dependable Computing and Communications Symposium,
International Conference on Dependable Systems and Networks (DSN),
June, 2004.)
- Improving
Processor Performance and Simulation Methodology,
Joshua J. Yi, Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 03-06,
December, 2003. (Ph.D. in Electrical Engineering thesis.)
-
The NanoBox Project: Exploring Fabrics of Self-Correcting Logic
Blocks for High Defect Rate Molecular Device Technologies
,
AJ KleinOsowski and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 03-05,
December, 2003.
(Presented at the
IEEE Annual Symposium on VLSI (ISVLSI),
February, 2004.)
-
Heuristics for Complexity-Effective Verification of a Cache Coherence
Protocol Implementation,
,
Dennis Abts, Ying Chen, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 03-04,
November, 2003.
-
Parallel Formulation of Spatial Auto-Regression,
B. Kazar, S. Shekhar, D. J. Lilja,
Army High-Performance Computing Research Center (AHPCRC)
Technical Report no. 2003-125, August 2003.
-
An Active Data-aware Cache Consistency Protocol for Highly-Scalable
Data-Shipping DBMS Architectures,
,
Keqiang Wu, Peng-fei Chuang, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 03-03,
August, 2003.
(Presented at the ACM International Conference on Computing Frontiers,
April, 2004.)
-
The NanoBox: A Self-Correcting Logic Block for Emerging Process
Technologies with High Defect Rates
,
AJ KleinOsowski, Priyadarshini Ranganath, Mahesh Subramony,
Vijay Rangarajan, Kevin KleinOsowski, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 03-02,
June, 2003.
-
"Address Correlation: Exceeding the Limits of Locality,"
Resit Sendag, Peng-fei Chuang, and David J. Lilja,
Computer
Architecture Letters,
Volume 2,
May 2003.
-
"So Many States, So Little Time: Verifying Memory Coherence in the Cray X1,"
Dennis Abts, Steve Scott, and David J. Lilja,
International Parallel and Distributed Processing Symposium (IPDPS),
April, 2003.
-
The Effect of Executing Mispredicted Load Instructions in a Speculative
Multithreaded Architecture
,
Resit Sendag, Ying Chen, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-11,
November, 2002.
(Presented at the
Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC),
held in conjunction with the
International Symposium on Microarchitecture, 2002.)
-
The Spatial Characteristics of Load Instructions
,
Joshua J. Yi, Resit Sendag, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-10,
October, 2002.
-
Using Incorrect Speculation to Prefetch Data in
a Concurrent Multithreaded Processor
,
Ying Chen, Resit Sendag, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-09,
October, 2002.
(An abridged
version
of this paper was presented at the
International Parallel and Distributed Processing Symposium (IPDPS),
April, 2003.)
-
``
MinneSPEC: A New SPEC Benchmark Workload for
Simulation-Based Computer Architecture Research
'',
AJ KleinOsowski and David J. Lilja,
Computer
Architecture Letters,
Volume 1,
May, 2002.
(Also referenced as,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-08,
October, 2002.)
-
A Statistically Rigorous Approach for Improving Simulation Methodology
,
Joshua J. Yi, David J. Lilja, and Douglas M. Hawkins,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-07,
September, 2002.
(An abridged
version
of this paper was presented at the International Symposium on
High-Performance Computer Architecture (HPCA),
February, 2003.)
-
Improving Processor Performance by Simplifying and Bypassing
Trivial Computations,
,
Joshua J. Yi and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-06,
June, 2002.
(An
abridged version
was presented at the International Conference on Computer Design (ICCD),
September, 2002.)
-
Exploiting the Prefetching Effect Provided by Executing
Mispredicted Load Instructions
,
Resit Sendag, David J. Lilja, and Steven R. Kunkel,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-05,
May, 2002.
(Presented at the ACM Euro-Par Conference,
August, 2002.)
-
Performance of Two-Dimensional Data Models for I/O Limited
Non-Numeric Applications
,
George G. Gorbatenko and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-04,
February, 2002.
-
Fault-Tolerant NanoBoxes for Designing Computers
Using Molecular Nanotechnology
,
AJ KleinOsowski, Richard A. Kiehl, David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-03,
February, 2002.
-
Increasing Instruction-Level Parallelism
with Instruction Precomputation
,
Joshua J. Yi, Resit Sendag, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 02-01,
February, 2002.
(Presented at the ACM Euro-Par Conference,
August, 2002.)
-
Using Hyperprediction to Compensate for Delayed Updates in Value Predictors
,
Qing Zhao, Sang-Jeong Lee, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 01-02,
June, 2001.
-
An Analysis of the Potential for Global Level Value Reuse
in the SPEC95 and SPEC2000 Benchmarks
,
Joshua J. Yi and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 01-01,
May, 2001.
-
Automatic Verification of Instruction Set Simulation Using
Synchronized State Comparison
,
Bob Glamm and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 00-10,
October, 2000.
(Presented at the Annual Simulation Symposium, April, 2001.)
-
Improving Value Prediction by Exploiting Both
Operand and Output Value Locality,
Youngsoo Choi, Joshua J. Yi, Jian Huang, and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 00-09,
July, 2000.
-
Compiler-Directed Static Classification of Value Locality Behavior,
Qing Zhao and David J. Lilja, Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 00-07,
July, 2000.
-
When All Else Fails, Guess: The Use of Speculative Multithreading
for High-Performance Computing,
David J. Lilja, Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 00-06,
June, 2000.
(To be presented at the International Conference on Advances in
Infrastructure for Electronic Business, Science,
and Education on the Internet,
L'Aquila, Italy, August, 2000.)
-
The SImulator for Multithreaded Computer Architecture,
Jian Huang, Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 00-05,
June, 2000.
- Improving
Processor Performance Through Compiler-Assisted Block Reuse,
Jian Huang, Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 00-04,
May, 2000. (Ph.D. in Computer Science thesis.)
-
Balancing Reuse Opportunities and Performance Gains
with Sub-Block Value Reuse
,
Jian Huang and David J. Lilja,
Laboratory for Advanced Research in Computing Technology and Compilers Technical
Report No. ARCTiC 02-02, February, 2002
(supercedes report No. ARCTiC 00-03, May, 2000).
(An abridged version of this paper was
presented at the International Conference on Parallel Architectures
and Compilation Techniques (PACT), October, 2000,
Exploring Sub-Block Value Reuse for Superscalar Processors,
Jian Huang and David J. Lilja.)
- JavaSpMT: A Speculative Thread Pipelining Parallelization Model for Java
Programs, Iffat H. Kazi and David J. Lilja, Laboratory for Advanced Research in Computing Technology and Compilers Technical
Report No. ARCTiC 99-10, November, 1999.
- The Superthreaded Multiprocessor: The Instruction Set Architecture and the
Parallel Execution Manager, Christoffer Amlo, Laboratory for Advanced Research in Computing Technology
and Compilers Technical Report No. ARCTiC 99-08, September, 1999. (M.S.E.E.
thesis.)
- Techniques for Obtaining High-Performance in Java Programs, Iffat H. Kazi, Howard H. Chen, Berdenia Stanley, and David J. Lilja, Laboratory
for Advanced Research in Computing Technology and Compilers Technical Report
No. ARCTiC 99-07, July 1999.
(Also appeared in
ACM Computing Surveys,
Vol. 32, No. 3, September, 2000, pp. 213-240.)
- ``The Superthreaded Processor Architecture,'' Jenn-Yuan Tsai, Jian Huang, Christoffer Amlo, David J. Lilja, and Pen-Chung
Yew, (published in) IEEE Transactions on Computers, Special Issue on Multithreaded Architectures
and Systems, September, 1999.
- Improving Instruction-Level Parallelism by Exploiting Global Value Locality, Jian Huang and David J. Lilja, High-Performance Parallel Computing Research
Group Technical Report No. HPPC-98-12, October 1998.
- Exploiting Basic Block Value Locality with Block Reuse, Jian Huang and David J. Lilja, High-Performance Parallel Computing Research
Group Technical Report No. HPPC-98-09, August 1998. (A version of this work
appeared in the International Symposium on High-Performance Computer Architecture, January 1999.)
- An Efficient Strategy for Developing a Simulator for a Novel Concurrent
Multithreaded Processor Architecture, Jian Huang and David J. Lilja, High-Performance Parallel Computing Research
Group Technical Report No. HPPC-98-08, August 1998. (A condensed version
appeared in the International Symposium on Modeling, Analysis and Simulation of Computer
and Telecommunication Systems, July 1998.)
- Coarse-Grained Speculative Execution in Shared-Memory Multiprocessors, Iffat H. Kazi and David J. Lilja, High-Performance Parallel Computing
Research Group Technical Report No. HPPC-98-07, August 1998. (A condensed
version appeared in the International Conference on Supercomputing, July 1998, pp. 93-100.)
-
Coarse-Grained Speculative Execution in Shared-Memory Multiprocessors
,
Iffat Hoque Kazi,
M.S. thesis, Department of Electrical and Computer Engineering,
May, 1998
(High-Performance Parallel Computing Research Group
Technical Report No. HPPC-98-04.)
-
``Integrating Parallelizing Compilation Technology and
rocessor Arcitecture for Cost-Effective Concurrent Multithreading,''
Jenn-Yuan Tsai, Zhenzhen Jiang, Zhiyuan Li, David J. Lilja, Xin Wang, Pen-Chung
Yew, Bixia Zheng, and Stephen J. Schwinn, Journal of Information Science and Engineering, Special Issue on Compiler
Techniques for High-Performance Computing, Vol. 14, No. 1, March 1998, pp. 205-222.
- Simulation and Analysis of Barrier Synchronization Methods, James R. Anderson, High-Performance Parallel Computing Research Group Technical
Report No. HPPC-95-04, August 1995.
- "A Distributed Hardware Mechanism for Process Synchronization on Shared-Bus
Multiprocessors," Donald Johnson, David J. Lilja, and John Riedl, International Conference on Parallel Processing, Volume II: Software, August 1994, pp. 268-275.
- "A Multiprocessor Architecture Combining Fine-Grained and Coarse-Grained
Parallelism Strategies," David J. Lilja, Parallel Computing, Vol. 20, No. 5, May 1994, pp. 729-751.
-
Evaluating Novel Memory System Alternatives for Speculative
Multithreaded Computer Systems
,
AJ KleinOsowski and David J. Lilja,
Laboratory for Advanced Research in Computing
Technology and Compilers Technical Report No. ARCTiC 01-04,
October, 2001.
-
A Language-Theoretic Approach to Specifying and Verifying
Multiprocessor Cache Coherence Protocols,
Dennis Abts, David J. Lilja, and Steve Scott,
Laboratory for Advanced Research in Computing Technology and Compilers
Technical Report No. ARCTiC 00-08, July, 2000.
-
Toward
Complexity-Effective Verification: A Case Study of the Cray SV2 Cache
Coherence Protocol, Dennis Abts, David J. Lilja, and Steve Scott,
Laboratory for Advanced Research in Computing Technology and Compilers
Technical Report No. ARCTiC 00-02, May 2000.
-
A Balanced Approach to High-Level Verification: Performance
Trade-offs in Verifying Large-Scale Multiprocessors,
Dennis Abts, Mike Roberts, and David J. Lilja,
Laboratory for Advanced Research in Computing Technology and
Compilers Technical Report No. ARCTiC 99-09, October 1999.
(Presented at the International Conference on Parallel Processing,
August, 2000.)
-
Dimensions
of Verifying the Hardware-Software Interface in a Shared-Memory Multiprocessor,
Dennis Abts, David J. Lilja, Abdulla Bataineh, and Steve Scott, Laboratory
for Advanced Research in Computing Technology and Compilers Technical Report
No. ARCTiC 99-04, May 1999.
-
A Compiler-Assisted
Data Prefetch Controller, Steven P. VanderWiel and David J. Lilja,
Laboratory for Advanced Research in Computing Technology and Compilers
Technical Report No. ARCTiC 99-05, May 1999. (Presented at the International
Conference on Computer Design, October, 1999.)
-
Masking
Memory Access Latency with a Compiler-Assisted Data Prefetch Controller,
Steven P. VanderWiel, Electrical Engineering Ph.D. thesis, University of
Minnesota, Laboratory for Advanced Research in Computing Technology and
Compilers Technical Report No. ARCTiC 98-13, September, 1998.
-
The Implementation
Impact of State-Based Priority Information in a Shared-Memory Cache Replacement
Policy, Farnaz Mounes-Toussi, Kerry Imming, David Krolak, and David
J. Lilja, High-Performance Parallel Computing Research Group Technical
Report No. HPPC-98-05, May 1998.
-
``The Effect
of Using State-Based Priority Information in a Shared-Memory Multiprocessor
Cache Replacement Policy'', Farnaz Mounes-Toussi and David J. Lilja,
International Conference on Parallel Processing, Minneapolis, August
1998. (Also High-Performance
Parallel Computing Research Group Technical Report No. HPPC-97-11, November
1997).
-
An Implementation
of a Cache Coherence Protocol on an ATM-Based Multiprocessor System,
JunSeong Kim and David J. Lilja, High-Performance Parallel Computing Research
Group Technical Report No. HPPC-96-06, October 1996.
-
When Caches Are
Not Enough: Data Prefetching Techniques, Steven VanderWiel and David
J. Lilja, IEEE Computer, Vol. 30, No. 7, July 1997, pp. 23-30. (Expanded
version -- High-Performance Parallel Computing Research Group Technical
Report no. HPPC-96-05, October 1996.)
-
``Write
Buffer Design for Cache-Coherent Shared-Memory Multiprocessors,'' Farnaz
Mounes-Toussi and David J. Lilja, International Conference on Computer
Design, October 1995, pp. 506-511.
-
"Compiler
Assistance for Directory-Based Cache Coherence Enforcement," David
J. Lilja, Workshop on Challenges for Parallel Processing, International
Conference on Parallel Processing, Oconomowoc, Wisconsin, August 1995,
pp. 133-138.
-
"The Potential
of Compile-Time Analysis to Adapt the Cache Coherence Enforcement Strategy
to the Data Sharing Characteristics," Farnaz Mounes-Toussi and David
J. Lilja, IEEE Transactions on Parallel and Distributed Systems.
Vol. 6, No. 5, May 1995, pp. 470-481.
-
Using
Compiler Assistance to Reduce the Network Traffic Requirements of a Directory-Based
Cache Coherence Mechanism, Zhiyuan Li, Farnaz Mounes-Toussi, and
David J. Lilja, High-Performance Parallel Computing Research Group Technical
Report No. HPPC-95-01, January 1995.
-
Reducing
the Impact of False-Sharing Using a Write-Through Cache with Partial Block
Invalidation, Farnaz Mounes-Toussi and David J. Lilja, High-Performance
Parallel Computing Research Group Technical Report No. HPPC-94-15, December
1994.
-
"A
Superassociative Tagged Cache Coherence Directory," David J. Lilja
and Shanthi Ambalavanan, International Conference on Computer Design,
October 1994, pp. 42-45. (
[extended version])
-
"A Compiler-Assisted
Scheme for Adaptive Cache Coherence Enforcement," Trung N. Nguyen,
Farnaz Mounes-Toussi, David J. Lilja, and Zhiyuan Li, IFIP International
Conference on Parallel Architectures and Compilation Techniques, August
1994, pp. 69-78.
-
"An
Evaluation of a Compiler Optimization for Improving the Performance of
a Coherence Directory," Farnaz Mounes-Toussi, David J. Lilja, and Zhiyuan
Li, ACM International Conference on Supercomputing, July 1994, pp.
75-84.
-
"Performance
Limits of Compiler-Directed Multiprocessor Cache Coherence Enforcement,"
Farnaz Mounes-Toussi and David J. Lilja, in The Interaction of Compilation
Technology and Computer Architecture, D. J. Lilja and P. L. Bird (eds.),
Kluwer Academic Publishers, Boston, MA, 1994, pp. 161-190.
-
"Improving
Memory Utilization in Cache Coherence Directories," David J. Lilja
and Pen-Chung Yew, IEEE Transactions on Parallel and Distributed Systems,
Vol. 4, No. 10, October 1993, pp. 1130-1146.
-
"Cache
Coherence in Large-Scale Shared-Memory Multiprocessors: Issues and Comparisons,"
David J. Lilja, ACM Computing Surveys, Vol. 25, No. 3, September
1993, pp. 303-338.
-
Compiler
Support for the Efficient Use of Cache Coherence Directories, Trung
N. Nguyen, Zhiyuan Li, and David J. Lilja, High-Performance Parallel Computing
Research Group Technical Report No. HPPC-94-19, December 1994. (Also appeared
as "Efficient Use of Dynamically Tagged Directories Through Compiler Analysis,"
Trung N. Nguyen, Zhiyuan Li, and David J. Lilja, International Conference
on Parallel Processing, Volume II: Software, August 1993, pp. 112-119.)
- ``Adapting
the SPEC 2000 Benchmark Suite for Simulation-Based
Computer Architecture Research'',
AJ KleinOsowski, John Flynn, Nancy Meares, and David J. Lilja,
Workshop on Workload Characterization,
International Conference on Computer Design,
September, 2000.
- ``JaViz: A Client/Server Java Profiling Tool,'' Iffat H. Kazi, Davis P. Jose, Badis Ben-Hamida, Chris J. Hescott, Chris
Kwok, Joseph Konstan, David J. Lilja, and Pen-Chung Yew, IBM Systems Journal, Volume 39, Number 1, 2000, pp. 96-117.
- Communication Overhead of MPI, PVM, and Sckt Library, Michael Kobler, JunSeong Kim, and David J. Lilja, High-Performance Parallel
Computing Research Group Technical Report No. HPPC-98-06, July 1998.
- A System Area Network Characterization in a Commercial Cluster, Richard Charles Booth, M.S. Thesis, Department of Electrical and Computer
Engineering, University of Minnesota, May 1998.
- Characterization of Communication Patterns in Message-Passing Parallel Scientific
Application Programs, JunSeong Kim and David J. Lilja, High-Performance Parallel Computing Research
Group Technical Report No. HPPC-97-10, October 1997. (Presented at the Workshop on Communication, Architecture, and Applications for Network-based
Parallel Computing, International Symposium on High Performance Computer
Architecture, February 1998, pp. 202-216 and Lecture Notes in Computer Science, Volume 1362, Spring-Verlag, 1998.)
- ``Complexity and Performance in Parallel Programming Languages,'' Steven VanderWiel, Daphna Nathanson, and David J. Lilja, International Workshop on High-Level Parallel Programming Models and Supportive
Environments, International Parallel Processing Symposium, April 1997, pp. 3-12.
- Performance and Program Complexity in Contemporary Network-based Parallel
Computing Systems, Steven VanderWiel, Dafna Nathanson, and David J. Lilja, High-Performance
Parallel Computing Research Group Technical Report No. HPPC-96-02, March
1996.
- "A Data Parallel Implementation of the TRFD Program from the Perfect Benchmarks," David J. Lilja and Jonathan Schmitt, EUROSIM International Conference on Massively Parallel Processing Applications
and Development, Delft, The Netherlands, June 1994, pp. 355-362.
-
Dynamically Adapting to System Load and Program Behavior
in Multiprogrammed Multiprocessor Systems,
,
Iffat H. Kazi and David J. Lilja,
High-Performance Parallel Computing Research Group
Technical Report No. HPPC-00-12, September, 2000.
-
A Dynamically Adaptive Parallelization Model
Based on Speculative Multithreading
,
Iffat Hoque Kazi,
Ph.D. thesis, Department of Electrical and Computer Engineering,
September, 2000
(High-Performance Parallel Computing Research Group
Technical Report No. HPPC-00-11.)
- A Comprehensive Dynamic Processor Allocation Scheme for Multiprogrammed
Multiprocessor Systems, Iffat H. Kazi and David J. Lilja, Laboratory for Advanced Research in Computing Technology and Compilers Technical Report, No. ARCTiC 00-01, February, 2000.
- Scheduling Multiple Heterogeneous Networks to Reduce Communication Costs
in Distributed Parallel Computing Systems, JunSeong Kim, Ph.D. in Electrical Engineering thesis, January 1999 (High-Performance
Parallel Computing Research Group Technical Report No. HPPC-99-03.)
- A Network Status Predictor to Support Dynamic Scheduling in Network-Based
Computing Systems, JunSeong Kim and David J. Lilja, High-Performance Parallel Computing Research
Group Technical Report No. HPPC-98-11, September 1998.
- Dynamic Processor Allocation with the Solaris Operating System, Kelvin K. Yue and David J. Lilja, High-Performance Parallel Computing
Research Group Technical Report No. HPPC-97-09, September 1997. (A condensed
version of this paper appeared at the International Parallel Processing Symposium, March 1998, pp. 392-397.)
- ``Utilizing Heterogeneous Networks in Distributed Parallel Computing Systems,'' JunSeong Kim and David J. Lilja, International Conference on High-Performance Distributed Computing, August 1997, pp. 336-345.
- ``Exploiting Multiple Heterogeneous Networks to Reduce Communication Costs
in Parallel Programs,'' JunSeong Kim and David J. Lilja, Heterogeneous Computing Workshop, International Parallel Processing Symposium, April 1997, pp. 83-95.
- "Performance Analysis and Prediction of Processor Scheduling Strategies
in Multiprogrammed Shared-Memory Multiprocessors," Kelvin K. Yue and David J. Lilja, International Conference on Parallel Processing, August 1996, pp. III:70-78.
- Performance Issues in Parallel Loop Scheduling for Multiprogrammed Multiprocessors, Kelvin K. Yue, Ph.D. thesis, Department of Computer Science, University
of Minnesota, Minneapolis, June 1996 (770 Kbytes).
- ``Designing Multiprocessor Scheduling Algorithms Using a Distributed Genetic
Algorithm System,'' Kelvin K. Yue and David J. Lilja, Evolutionary Algorithms in Engineering Applications, Dipankar Dasgupta and Zbigniew Michalewicz (eds.), Springer Verlag, March
1997, pp. 207-222.
- ``Dynamic Scheduling Strategies for Shared-Memory Multiprocessors,'' Babak Hamidzadeh and David J. Lilja, International Conference on Distributed Computing Systems, May 1996, pp. 208-215.
- "Efficient Execution of Parallel Applications in Multiprogrammed Multiprocessor
Systems," Kelvin K. Yue and David J. Lilja, International Parallel Processing Symposium, April 1996, pp. 448-456.
- "Dynamic Scheduling Techniques for Heterogeneous Computing Systems," Babak Hamidzadeh, David J. Lilja, and Yacine Atif, Concurreny: Practice and Experience, Special Issue on Resource Management
in Parallel and Distributed Systems, Vol. 7, No. 7, October 1995, pp. 633-652.
- "Parallel Loop Scheduling for High-Performance Computers," Kelvin K. Yue and David J. Lilja, High Performance Computing: Technology, Methods, and Applications, J. Dongarra, L. Grandinetti, G. Joubert and J. Kowalik (eds.), Elsevier
Publishing Company, Amsterdam, September 1995, pp.243-264.
- "Parameter Estimation for a Generalized Parallel Loop Scheduling Algorithm," Kelvin K. Yue and David J. Lilja, Practical Handbook of Genetic Algorithms, Volume 2: New Frontiers, Lance D. Chambers (ed.), CRC Press, Inc., Boca Raton, Florida, August 1995,
pp. 155-171.
- Performance Evaluation of Different Scheduling Schemes on Multiprocessor
Architectures (M.S. Thesis), Arundhati Kalavade, High-Performance Parallel Computing Research Group Technical
Report No. HPPC-95-03, June 1995.
- "Partitioning Tasks Between a Pair of Interconnected Heterogeneous Processors:
A Case Study," David J. Lilja, Concurrency: Practice and Experience, Vol. 7, No. 3, May 1995, pp. 209-223. [short version]
- "Loop-Level Process Control: An Effective Processor Allocation Policy for
Multiprogrammed Shared-Memory Multiprocessors," Kelvin K. Yue and David J. Lilja, Workshop on Job Scheduling Strategies for Parallel Processing, International
Parallel Processing Symposium, D. G. Feitelson and L. Rudolph (eds.), Springer-Verlag Lecture Notes in
Computer Science, Vol. 949, April 1995, pp. 182-199.
- Categorizing Parallel Loops Based on Iteration Execution Time Variances, Kelvin K. Yue and David J. Lilja, High-Performance Parallel Computing Research
Group Technical Report No. HPPC-94-13, November 1994.
- "Self-Adjusting Scheduling: An On-Line Optimization Technique for Locality
Management and Load Balancing," Babak Hamidzadeh and David J. Lilja, International Conference on Parallel Processing, Volume II: Software, August 1994, pp. 39-46.
- "The Impact of Parallel Loop Scheduling Strategies on Prefetching in a Shared-Memory
Multiprocessor," David J. Lilja, IEEE Transactions on Parallel and Distributed Systems, Vol. 5, No. 6, June 1994, pp. 573-584.
- "Exploiting the Parallelism Available in Loops," David J. Lilja, IEEE Computer, Vol. 27, No. 2, February 1994, pp. 13-26.
- ``Education at a Distance: A Report From the Front,'' David J. Lilja, Workshop on Computer Architecture Education at the International Symposium
on High-Performance Computer Architecture, January 1999.
- ``Education at a Distance: A Report From the Front,'' David J. Lilja, Workshop on Computer Architecture Education at the International Symposium
on High-Performance Computer Architecture, January 1999.
- ``Suggestions for Teaching the Engineering Research Process,'' American Society for Engineering Education Annual Conference, New Engineering
Educators Division, June 1997.
- "Computer Architecture Research: Teaching the Basic Skills," David J. Lilja, Workshop on Computer Architecture Education at the International Symposium
on High-Performance Computer Architecture, February 3, 1996.
- "Trends in High-Performance Computer Architecture," David J. Lilja, IEEE Computer Society, Minneapolis, April, 1996.
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