Designing Digital Computer Systems with Verilog

David J. Lilja and Sachin S. Sapatnekar
Cambridge University Press, New York, NY, 2005
ISBN 0-521-82866-X


If you find any errors in the book, please contact one of the authors (click through to their web sites using the links above).

The following corrections should be made to the book :

  1. p. 47, Sec. 3.2.5, 3rd sentence -- "It also may useful to have ..." should be "It also may be useful to have ..."
  2. p. 51, Figure 3.2 -- In the top half of the figure, the bit field from "10...0" should have the value "000 0000 0000".
  3. p. 85, Figure 5.1 -- The first comment "A test program that simply loops 'count' number of times." may be a bit confusing. The "ble" instruction branches to the label "back" "count" times. However, the statements within the loop are executed ("count" + 1) times.
  4. p. 109, Figure 7.1 -- The box labeled "Cond" between stages 2 and 3 should be "Cond3" and the box labeled "Cond" between stages 3 and 4 should be "Cond4".
  5. p. 109, Figure 7.1 -- The output of register Z4 should be an input to both Stage 3 (EX) and Stage 1 (IF).
  6. p. 111, Figure 7.3 -- Input 0 of the MUX feeding register MD3 should be connected to the "Read Port 2" output of the register file.
  7. pp. 134, 137, 141, 145 -- In the "Detailed operation" section for the ADD, CMP, MOV, and SUB instructions, the inputs for the "setcc" task should be (op1, op2, R[rdst], subt) to match the Verilog implementation distributed on this web site.