Designing Digital Computer Systems with Verilog

David J. Lilja and Sachin S. Sapatnekar
Cambridge University Press, New York, NY, 2005
ISBN 0-521-82866-X

Designing Digital Computer Systems with Verilog serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model, and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioral and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practicing engineers.


A list of corrections for the book


Supplemental Materials

This web site contains a variety of supplemental materials for use with this book. This material includes Verilog source code for the examples in the book, the Verilog source code for the behavioral and pipelined models of VeSPA, the source code for the VASM assembler, and some test programs. We also have included some material supplied by people who have developed some additional tools that you may find useful when working with VeSPA.

We are continually looking for new VeSPA-related material to add to this page. Please contact us through the links to our web sites above if you have some material that you would like us to consider including.

book cover